Features&nbsp

True parallel bit-error-rate measurement across 8 lanes at up to 28.05 Gbps per lane

Fully-synthesized integrated jitter injection on all lanes

Programmable output voltage for receiver stress test applications

Flexible pre-emphasis and equalization

Flexible loopback support per lane

Hardware clock recovery per lane

State of the art programming environment based on the highly intuitive Python language

Reconfigurable, protocol customization (on request)

Applications&nbsp

Parallel PHY validation of serial bus standards

Interface tests of electrical/optical media

At-speed production tests

Name	SV2D-32
Description	Direct Attach SerDes Test Module
Tx Channels	8
Rx Channels	8
Min Data Rate	19.6 Gbps
Max Data Rate	32 Gbps
Clock Inputs	1
User Programmable Pattern Memory	Per channel PRBS polynomials 5-31, arbitrary user patterns, nested pattern sequencer loops
Pattern Capability	Per channel PRBS polynomials 5-31, arbitrary user patterns, nested pattern sequencer loops
Equalization & Clock Recovery	Analog CDR
Series	SV2C Series
Configurations	Instrument & Software

SV2D-32

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