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SV2D-28

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Quick Overview

Direct Attach SerDes Test Module

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More Information
name	SV2D-28
Description	Direct Attach SerDes Test Module
Max Data Rate	28.05 Gbps
Min Data Rate	19.6 Gbps
Tx Channels	8
Rx Channels	8
Clock Inputs	1
Equalization & Clock Recovery	Analog CDR
Pattern Capability	Per channel PRBS polynomials 5-31, arbitrary user patterns, nested pattern sequencer loops
User Programmable Pattern Memory	1 Mbits
Configuration	Instrument & Software

Quick Overview

Features

True parallel bit-error-rate measurement across 8 lanes at up to 28.05 Gbps per lane

Fully-synthesized integrated jitter injection on all lanes

Programmable output voltage for receiver stress test applications

Flexible pre-emphasis and equalization

Flexible loopback support per lane

Hardware clock recovery per lane

State of the art programming environment based on the highly intuitive Python language

Reconfigurable, protocol customization (on request)

Applications

Parallel PHY validation of serial bus standards

Interface tests of electrical/optical media

At-speed production tests

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Company Info

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+42 98 9876

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